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Hardware/software co-design of digital telecommunication systems., , , , , and . Proc. IEEE, 85 (3): 391-418 (1997)Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies., , , , , , , and . IEEE J. Solid State Circuits, 38 (7): 1250-1260 (2003)Interprocessor communication in synchronous multiprocessor digital signal processing chips., , , and . IEEE Trans. Acoust. Speech Signal Process., 37 (12): 1816-1828 (1989)Security and performance optimization of a new DES data encryption chip., , , and . IEEE J. Solid State Circuits, 23 (3): 647-656 (June 1988)A flexible module library for custom DSP applications in a multiprocessor environment., , , and . IEEE J. Solid State Circuits, 25 (3): 720-729 (June 1990)Design of a process-tolerant cell library for regular structures using symbolic layout and hierarchical compaction., , and . IEEE J. Solid State Circuits, 23 (3): 714-721 (June 1988)CAMELEON: a process-tolerant symbolic layout system., , and . IEEE J. Solid State Circuits, 23 (3): 705-713 (June 1988)Estimation of typical power of synchronous CMOS circuits using a hierarchy of simulators., , , and . IEEE J. Solid State Circuits, 28 (1): 26-39 (January 1993)
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